Digital Design & Verification.

From a design to its behavior

Digital design becomes more concrete when a functional model is compared with an implementation that includes gate delays. This coursework connects RTL simulation, timing constraints, gate level simulation, and verification.

What the work covers

• Running and comparing RTL and gate level simulations.
• Applying clock constraints and inspecting timing reports.
• Using delay annotation to study implementation behavior.
• Checking how input timing affects observed waveforms.
• Examining assertion, branch, statement, and toggle coverage.

The connection to my background

At Synopsys Lanka, I worked on power estimation and signoff validation for PrimePower. These laboratory exercises build on my interest in relating tool output to the behavior of the underlying design.

What I focus on

I am interested in what a result actually demonstrates: the assumptions behind a simulation, what timing information has been included, and which behaviors have been exercised by a test.

The waveform above is illustrative. It is not an exported simulation trace or a claim about a particular design’s timing.